Stromasys Launches Charon-PAR 4.0 – A Major Advancement to Its PA-RISC Emulator

Stromasys announces a major milestone for its PA-RISC emulation technology, releasing a new version designed to boost ...
The Floridian

Open Chips, Big Stakes: A Guide to RISC-V

Even in a dysfunctional and divided political climate, both a Republican and Democratic-run Washington have invested significant capita ...
Design And Reuse

Fabless Startup Aheesa Tapes Out First Indian RISC-V Network SoC

Indian fabless semiconductor startup Aheesa Digital Innovations has completed the tape-out of a domestically designed RISC-V-based broadband networking SoC, called VIHAAN-I, targeting optical fiber ...
Design And Reuse

MIPS accelerates the development timeline of the RISC-V NPU S8200, integrating Synopsys ARC IP to transform into a "physical AI" computing platform.

A veteran processor architect striving to regain its glory in the RISC-V architecture arena.MIPSMIPS has been making frequent moves recently. It announced that it will accelerate its designs for edge ...
Digi Times

MIPS expands RISC-V processor platform with ARC IP integration

MIPS is repositioning itself within the RISC-V ecosystem following the integration of the ARC Processor IP business acquired from Synopsys, moving beyond a CPU-centric model toward a broader processor ...
Network World

RISC-V chip designer SiFive integrates Nvidia NVLink Fusion to power AI data centers

RISC-V pioneer SiFive has signed a deal with Nvidia to incorporate Nvidia NVLink Fusion into its data center products. The agreement means that SiFive will be able to connect its RISC-V CPUs to Nvidia ...
TechSpot

Milk-V Titan gives developers a plug-and-play RISC-V desktop

The takeaway: The RISC-V architecture's transition from theory to tangible desktop hardware continues with the arrival of the Milk-V Titan, a mini-ITX motherboard built around the UltraRISC UR-DP1000 ...
Semiconductor Engineering

Performant Side-Channel Resistant RISC-V Core to Secure Neural Network Inference (Northeastern Univ.)

A new technical paper titled “PermuteV: A Performant Side-channel-Resistant RISC-V Core Securing Edge AI Inference” was published by researchers at Northeastern University. “Edge AI inference is ...
Digi Times

Qualcomm, Google bet big on RISC-V for AI dominance

As AI drives demand for advanced computing infrastructure, chip architectures are at a crossroads. While proprietary instruction set architectures (ISAs) like x86 and Arm dominate the market, their ...
EDN

RISC-V Summit spurs new round of automotive support

The adoption of RISC-V with open standards in automotive applications continues to accelerate, leveraging its flexibility and scalability, particularly benefiting the automotive industry’s shift to ...
IEEE

BnnRV: Hardware and Software Optimizations for Weight Sampling in Bayesian Neural Networks on Edge RISC-V Cores

Abstract: Bayesian Neural Networks (BNN) allow prediction uncertainty estimation, making them a more suitable option for safety-critical applications. However, in BNNs, the forward-pass computational ...
Electronic Specifier

MIPS launches RISC-V processor to power next wave of ‘Physical AI’ systems

The MIPS I8500, unveiled at GlobalFoundries’ Technology Summit in Munich, is the company’s third-generation, four-thread-per-core processor built on the open RISC-V instruction set architecture. The ...