Electronic Design

Efficient eye diagram testing in DDR3/DDR4 system designs

Learn more with our material for efficient eye diagram testing in DDR3/DDR4 system designs. Compliance testing is essential to ensuring that dynamic random access memory (DRAM) signals meet the JEDEC ...
Electronic Design

Eye-Diagram Analysis Speeds DDR SDRAM Validation

Double-data-rate synchronous dynamic random access memory (DDR SDRAM) physical-layer testing is a crucial step in making sure devices comply with the JEDEC specification. The ultimate goal is to ...
Business Wire

Keysight Introduces Comprehensive LPDDR6 Solution for End-to-End Memory Design and Test Workflows

Delivers complete design and validation solution for Low-Power Double Data Rate 6 (LPDDR6) memory in mobile, client computing, and AI applications. Supports JEDEC’s ongoing development of the new ...
EDN

How to test high-speed memory with non-intrusive embedded instruments, Part 2

Having explained in part 1 the nature of the memory test challenge in the industry today, this article discusses non-intrusive debug and test methods based on embedded instruments and how these ...